The present invention relates to a physical quantity distribution detector, a physical information acquiring method, and a physical information acquiring device. More specifically, the invention relates to a technology for acquiring information for predetermined purposes that is suitable in using a portion for physical quantity distribution detection (a physical quantity distribution detector) such as a solid-state imaging device that has plural unit components, which have sensitivity to electromagnetic waves inputted from the outside such light and radiations, arranged therein and is capable of reading out a physical quantity distribution converted into an electric signal by the unit components as the electronic signal. In particular, the invention relates to a noise resistance property in transmitting an analog signal detected by a detector to an output side directly as the analog signal or after converting the analog signal into digital data.
Physical quantity distribution detecting semiconductor devices having plural unit components (e.g., pixels) arranged in a line shape of a matrix shape are used in various fields. The unit components have sensitivity to a physical quantity change of light and electromagnetic waves inputted from the outside such as radiations or pressures (by contact or the like).
As an example, in the field of video equipment, solid-state imaging devices are used. The solid-state imaging devices use imaging devices of a Charge Coupled Device (CCD) type or a Metal Oxide Semiconductor (MOS) or Complementary Metal-Oxide Semiconductor (CMOS) type that detect a change in light (an example of electromagnetic waves) that is an example of a physical quantity.
In the field of computer equipment, fingerprint authentication apparatuses and the like are used. The fingerprint authentication apparatuses detect an image of a fingerprint on the basis of a change in an electric characteristic based on a pressure or a change in an optical characteristic. The fingerprint authentication apparatuses and the like read out a physical quantity distribution converted into an electric signal by unit components (pixels in the solid-state imaging device) as the electric signal.
Among the solid-state imaging devices, there is amplification-type solid-state imaging device. The amplification-type solid-state imaging device includes pixels of an amplification-type solid-state imaging device (Active Pixel Sensor (APS); also referred to as gain cell or intra-pixel amplifier) constitution having a driving transistor for amplification in a pixel signal generator that generates a pixel signal corresponding to a signal charge generated by a charge generator. For example, many CMOS solid-state imaging devices adopt such a constitution (see, for example, Kazuya Yonemoto, “Basics and Applications of CCD/CMOS Image Sensor”, CQ Publishing Co., Ltd., Aug. 10, 2003, First edition, Chapters 6 and 7 (Non-Patent Document 1).
In such an amplification-type solid-state imaging device, in order to read out a pixel signal to the outside, address control is applied to an imaging area in which plural unit pixels are arranged and signals from the respective unit pixels are selected and read out in a determined order of addresses or arbitrarily. In other words, the amplification-type solid-state imaging device is an example of an address control type solid-state imaging device.
In the address control type solid-state imaging device, MOS transistors are used in, for example, a switching element that selects pixels and a switching element that reads out signal charges. The MOS transistors are also used in a horizontal scanning circuit and a vertical scanning circuit. The address control type solid-state imaging device has an advantage that it is possible to manufacture the switching elements and the imaging area in series.
For example, in the MOS solid-state imaging device, respective unit pixels have MOS transistors. The MOS solid-state imaging device reads out signal charges accumulated in pixels by photoelectric conversion to a pixel signal generator, converts the signal charges into current signals or voltage signals, and outputs the current signals or the voltage signals.
For example, in an amplification-type solid-state imaging device that is a type of an X-Y address-type solid-state imaging device in which unit pixels are arranged in a matrix shape, pixels are constituted using active devices (MOS transistors) of a MOS structure or the like in order to give an amplification function to the pixels. In other words, signal charges (photoelectrons and holes) accumulated in photodiode serving as a photoelectric conversion element are amplified by the active device of a pixel signal generator and read out as image information.
In the X-Y address-type solid-state imaging device, for example, the imaging area includes a large number of pixel transistors arranged in a two-dimensional pixel shape. Accumulation of signal charges corresponding to incident light is started for each of lines (rows) or each of the pixels. Current signals or voltage signals based on the signal charges accumulated are read out in order from the respective pixels according to address designation. In the MOS (including CMOS) solid-state imaging device, a system for simultaneously accessing the pixels in one line and reading out pixel signals from the imaging area by a unit of row (hereinafter also referred to as row unit readout system or column readout system) is often used as an example of address control.
FIG. 14 is a schematic diagram of a solid-state imaging device 1 of the column readout system. The solid-state imaging device 1 includes a driving control unit 7 that has a horizontal scanning unit 12 and a vertical scanning unit 14 around an imaging area 10 of a pixel array structure in which plural unit pixels 3 are arranged in rows and columns. The driving control unit 7 includes, other than the horizontal scanning unit 12 and the vertical scanning unit 14, a timing control unit 11 of a Phase Lock Loop (PLL) constitution that receives a master clock CLK0 from the outside, generates various internal clocks, and controls the horizontal scanning unit 12, the vertical scanning unit 14, and the like. The driving control unit 7 also includes a column processor 20 serving as a signal processor that processes pixel signals outputted from the imaging area 10, a horizontal selection switch unit 60 that has selection switches (SW) 60a, a horizontal signal line 86, and an output unit 88.
In the imaging area 10, as an example, 1280 unit pixels 3 are arranged in a horizontal direction (H) and 960 unit pixels 3 are arranged in a vertical direction (V). The respective unit pixels 3 are connected to row control lines 15 controlled by the vertical scanning unit 14 and vertical signal lines 18 that transmit pixel signals to the column processor 20.
The column processor 20 includes column signal processors 22 including noise removing units 22a that have not-shown accumulation capacitors and use Correlated Double Sampling (CDS) processing and units (sample and hold (S/H) units) 22b that subject a signal to sample and hold (S/H).
With such a constitution, in one H period (e.g., 63.3 μs) for processing one row, a period for reading out a pixel signal from the imaging area 10 is about 8.5 μs and a period for horizontal transfer by the horizontal selection switch unit 60 is the remaining period of about 54.8 μs.
An analog pixel signal read out from the imaging area is converted into digital data by an Analog Digital Converter (an AD converter) when necessary. In the constitution in FIG. 14, as an example, the AD converter (ADC) is built in the output unit 88.
In general, the pixel signal is outputted in a form in which a signal component is added to a reset component. Thus, it is necessary to extract a true effective signal component by calculating a difference between a signal voltage corresponding to the reset component and a signal voltage corresponding to the signal component.
The same applies when an analog pixel signal is converted into digital data. Finally, it is necessary to convert a differential signal component of a signal voltage corresponding to a reset component and a signal voltage corresponding to a signal component into digital data. Therefore, various mechanisms for AD conversion have been proposed (see, for example, Non-Patent Document 1; W. Yang et. al., “An Integrated 800×600 CMOS Image System”, ISSCC Digest of Technical Papers, pp. 304-305, February 1999 (Non-Patent Document 2); Toshifumi Imamura, Yoshiko Yamamoto, “3. Study of High-speed/function CMOS Image Sensor”, [online], [retrieved Mar. 15, 2004], Internet URL:http://www.sankaken.gr.jp/project/iwataPJ/report/h12/h 12index.html (Non-Patent Document 3); Toshifumi Imamura, Yoshiko Yamamoto, Naoya Hasegawa, “3. Study of High-speed/function CMOS Image Sensor”, [online], [retrieved Mar. 15, 2004], Internet URL:http://www.sankaken.gr.jp/project/iwataPJ/report/h14/h14index.html (Non-Patent Document 4); and Oh-Bong Kwon et. al., “A Novel Double Slope Analog-to-Digital Converter for a High-Quality 640×480 CMOS Imaging System”, VL3-03 1999 IEEE p 335 to 338) (Non-Patent Document 5)).
For example, the Non-Patent Documents 1 to 5 disclose a mechanism for sequentially reading out signal outputs of pixels arranged in a matrix shape to vertical data lines for each row and, then, converting the signal outputs into digital data with an AD converter provided for each of the vertical data lines. Such an AD system will be hereinafter also referred to as a column ADC system.
In the mechanism for AD conversion (the column ADC system) disclosed in the Non-Patent Documents 1 to 5, to explain more in detail, a pixel signal from an imaging area and a voltage of a ramp waveform (a reference signal RAMP), a voltage value of which changes at a fixed inclination, are compared and time for the comparison processing is counted by a counter clock. Specifically, the count is started substantially simultaneously with start of the comparison and a value (digital data) of a counter representing a voltage of the ramp waveform at the time when an output of a comparator reverses is outputted, whereby pixel signals of respective vertical columns are converted into digital pixel data for each of the vertical columns.
FIG. 15 is a schematic diagram of a solid-state imaging device 1 of the column ADC system. The solid-state imaging device 1 includes a driving control unit 7 provided outside an imaging area 10, a column processor 20 that has a count processor (CNT) 23 and column AD circuits 24 arranged for each of vertical columns, a reference signal generator 26 including a Digital Analog Converter (DAC) that supplies a reference voltage for AD conversion to the column AD circuits 24 of the column processor 20, and an output unit 88 that has a function as a sense amplifier using digital signal processing.
The column AD circuits 24 include voltage comparators 242 that compare a reference voltage RAMP generated by the reference signal generator 26 and analog pixel signals obtained from unit pixels 3 through vertical data lines 18 (H1, H2, . . . ) for each of row control lines 15 (V1, V2, . . . ) and data storing units 244 including two sets of n latches (flip-flops) serving as memory devices that hold, for each bit data, a result obtained by counting time until the voltage comparators 242 complete the comparison processing using a count processor 23. The column AD circuit 24 has an n-bit AD conversion function. Since the column AD circuit 24 has the two sets of n latches, it is possible to hold data corresponding to a reset component and data corresponding to a signal component separately from each other.
A step-wise reference voltage RAMP generated by the reference signal generator 26 is commonly inputted to one input terminal of one of the voltage comparators 242 and one input terminals of the other voltage comparators 242. The vertical data lines 18 of vertical columns corresponding to the voltage comparators 242, respectively, are connected to the other input terminals of the voltage comparators 242. Pixel signal voltages from the imaging area 10 are separately inputted to the voltage comparators 242. Output signals of the voltage comparators 242 are supplied to data storing units 244.
The count processor 23 performs count processing on the basis of a counter clock CK0 corresponding to a master clock CLK0 (e.g., clock frequencies of both the clocks are equal) and supplies count outputs CK1, CK2, . . . , CKn commonly to the respective column AD circuits 24 of the column processor 20 together with the counter clock CK0 for synchronization.
In other words, wirings for the respective count outputs CK1, CK2, . . . , CKn from the count processor 23 are led to the respective latches of the data storing units 244 arranged for each of the vertical columns. Consequently, the column AD circuits 24 of the respective vertical columns commonly use the one count processor 23.
Output sides of the respective column AD circuits 24 are connected to a horizontal data line 86. The horizontal data line 86 has data lines for a 2n-bit width. Data are supplied to 2n sense amplifiers corresponding to not-shown respective output lines in the output unit 88. A not-shown subtraction circuit is provided in the output unit 88. The output unit 88 extracts true effective signal data by calculating a difference between data corresponding to a reset component and data corresponding to a signal component.
According to such a column ADC system, since AD conversion is performed in the respective columns (vertical columns), the column ADC system is advantageous for an increase in speed of readout and the AD conversion processing.